In an electrical communication bus in which a memory controller is coupled with a memory device such as a GDDR3 DRAM memory, the DRAMs are designed to train their drive impedance and termination impedance against a reference resistor. However, process variations and resolution may cause variations in the final DRAM training values. The variations may occur within a memory controller coupled to the DRAM if it trains in a similar manner, thereby causing a mismatch in DRAM and controller impedances.
Such mismatches may cause timing offsets due to the reference voltages not being properly aligned to the resulting data eye. The problem can occur specifically in a GDDR3 interface from a memory controller to a GDDR3 memory device. However, the problem also occurs in a number of other system and sub-system electrical communication buses. The offsets may result in reduced timing margins in such situations.
Accordingly, what is needed is an arrangement which couples a memory device and its memory controller during memory driver training to reduce mismatches through calibration of a DRAM driver with the memory controller.